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hn27c4000g series 524288-word 8-bit/262144-word 16-bit cmos uv erasable and programmable rom rev. 1 nov. 10, 1994 the hitachi hn27c4000 is a 4-mbit uv erasable and electrically programmable rom that is organized either as 524288-word 8 bit or as 262144-word 16 bit, featuring extra-high speed burst mode that gives two times faster 4-word or 8- byte serial access than normal. and also high speed and fast programming are served as well as the existing hitachi 4m device hn27c4096 and hn27c4001. fabricated on advanced fine process and high speed circuitry technique, hn27c4000 makes high speed access time and low power dissipation in either active or stand-by mode. therefore, it is suitable for all systems featuring high speed microprocessor such as the 80386, 80486, 68030, 68040 and so on. features organization: 524288-word 8-bit/262144- word 16-bit ( byte /v pp enables selection byte-wide or word-wide) high speed: access time 100 ns/120 ns/150 ns (max) burst access time 50 ns/60 ns/60 ns (max) low power dissipation: standby mode; 5 ? (typ), active mode; 150 mw/mhz (typ) fast high reliability page programming, fast high-reliability programming and option programming: program voltage; +12.5 v dc program time; 3.5 sec (min) (theoretical in page programming) inputs and outputs ttl compatible during both read and program modes pin arrangement: 40-pin eiaj standard pin compatible with hn62414/ hn62434 device identifier mode: manufacturer code and device code ade-203-311a (z)
pin arrangement 2 hn27c4000g series a17 a7 a6 a5 a4 a3 a2 a1 a0 ce v oe i/o0 i/o8 i/o1 i/o9 i/o2 i/o10 i/o3 i/o11 ss a8 a9 a10 a11 a12 a13 a14 a15 a16 byte/v v i/o15/a-1 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 v ss pp cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 hn27c4000g series (top view) ordering information access type no. time package HN27C4000G-10 100 ns 600-mil hn27c4000g-12 120 ns 40-pin cerdip hn27c4000g-15 150 ns (dg-40a) pin description pin name function a0 ?a17 address i/o0 ?i/o14 input/output i/o15/a-1 input/output/address ce chip enable oe output enable v cc power supply byte /v pp byte/word selection/ programming power supply v ss ground
block diagram mode selection pin ce oe a9 byte /v pp v cc i/o0 ?i/o7, i/o8 ?i/o14, i/o15/a-1 mode dg-40a (10) (12) (39) (31) (21) (13 ?20, 22 ?28, 29) read (x16 bit) v il v il xv ih v cc dout dout dout read (x8 bit) v il v il xv il v cc dout high-z v ih /v il output disable (x16 bit) v il v ih xv ih v cc high-z high-z high-z output disable (x8 bit) v il v ih xv il v cc high-z high-z v ih /v il 3 hn27c4000g series i/o0 : : : i/o15 x- decoder 2,048 x 2,048 memory matrix y-decoder ce oe input data control y-gating v cc v v ss h a0 a6 h : high threshold inverter a7 : : : : : : : : : : : : a17 pp . . . . . . . . . . . . .
mode selection (cont) pin ce oe a9 byte /v pp v cc i/o0 ?i/o7, i/o8 ?i/o14, i/o15/a-1 mode dg-40a (10) (12) (39) (31) (21) (13 ?20, 22 ?28, 29) standby v ih xxv ss ?v cc v cc high-z high-z high-z page page program set v ih v h *2 xv pp v cc high-z high-z high-z prog. page data latch v il v h *2 xv pp v cc din din din page program v il v ih xv pp v cc high-z high-z high-z page program verify v ih v il xv pp v cc dout dout dout page program reset v ih v ih xv cc v cc high-z high-z high-z word program v il v ih xv pp v cc din din din prog. program verify v ih v il xv pp v cc dout dout dout optional verify v il v il xv pp v cc dout dout dout program inhibit v ih v ih xv pp v cc high-z high-z high-z identifier v il v il v h *2 v ss ?v cc v cc code code code notes: 1. x: don? care. 2. v h : 12.0 v 0.5 v absolute maximum ratings item symbol value unit all input and output voltages *1 vin, vout ?.6 *2 to +7.0 v voltage on pin a9 and oe v id ?.6 *2 to +13.0 v v pp voltage *1 v pp ?.6 to +13.5 v v cc voltage *1 v cc ?.6 to +7.0 v operating temperature range topr 0 to +70 ? storage temperature range *3 tstg ?5 to +125 ? storage temperature under bias tbias ?0 to +80 ? notes: 1. relative to v ss . 2. vin, vout, v id min = ?.0 v for pulse width 20 ns 3. storage temperature range of device before programming. 4 hn27c4000g series
capacitance (ta = 25?, f = 1 mhz) item symbol min typ max unit test conditions notes input capacitance cin 12 pf vin = 0 v except byte /v pp output capacitance cout 20 pf vout = 0 v read operation dc characteristics (v cc = 5 v 10%, v pp = v ss to v cc , ta = 0 to +70?) item symbol min typ max unit test conditions input leakage current i li 2 a vin = 5.5 v output leakage current i lo 2 a vout = 5.5 v/0.45 v v pp current i pp1 1 20 ? v pp = 5.5 v standby v cc current i sb1 1 ma ce = v ih i sb2 ? 20a ce = v cc 0.3 v operating v cc current i cc1 35 ma iout = 0 ma, f = 1 mhz i cc2 120 ma iout = 0 ma, f = 10 mhz input voltage v il ?.3 *1 0.8 v v ih 2.2 v cc v + 1 *2 output voltage v ol 0.45 v i ol = 2.1 ma v oh 2.4 v i oh = ?00 ? notes: 1. v il min = ?.0 v for pulse width 50 ns v il min = ?.0 v for pulse width 20 ns 2. v ih max = v cc +1.5 v for pulse width 20 ns if v ih is over the specified maximum value, read operation cannot be guaranteed. 5 hn27c4000g series
ac characteristics (v cc = 5 v 10%, v pp = v ss to v cc , ta = 0 to +70?) test conditions input pulse levels: 0.45 to 2.4 v input rise and fall times: 10 ns output load: 1 ttl gate +100 pf reference levels for measuring timing: 0.8 v, 2.0 v hn27c4000 hn27c4000 hn27c4000 -10 -12 -15 item symbol min max min max min max unit test conditions address to output delay t acc 100 120 150 ns ce = oe = v il ce to output delay t ce 100 120 150 ns oe = v il oe to output delay t oe 60 60 70 ns ce = v il burst address to t bac 50 60 60 ns ce = v il output delay oe high to output float *1 t df 0 35 0 40 0 50 ns ce = v il address to output hold t oh 555ns ce = oe = v il note: 1. t df is defined as the time at which the output achieves the open circuit condition and data is no longer driven. read timing waveform 6 hn27c4000g series address ce oe data out data out valid t acc t ce t oe t oh t df standby mode active mode standby mode
read timing waveform (burst access mode) in burst access mode, fast read-out of 4 word data is selected by address a0, a1. (valid only for read 16 mode) 7 hn27c4000g series t bac t ce t oe t bac t bac t bac t oh t oh t oh t oh valid output valid output valid output valid output a2 to a17 oe ce a0, a1 data out t acc
in burst access mode, fast read-out of 8 byte data is selected by address a-1, a0, a1. (valid only for read 8 mode) 8 hn27c4000g series t bac t ce t oe t bac t bac t bac t valid output a2 to a17 oe ce a-1, a0, a1 data out t acc valid output valid output valid output valid output valid output valid output valid output t t t t t t t t bac t bac t bac t bac oh oh oh oh oh oh oh oh
fast high-reliability page programming this device can be applied the high performance page programming algorithm shown in the following flowchart. this algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. page program set apply 12 v to oe pin after applying 12.5 v to v pp to set a page program mode. the device operates in a page program mode until reset. page program reset set v pp to v cc level or less to reset a page program mode. 9 hn27c4000g series start set page prog latch mode v = 12.5 ?0.3 v v = 6.25 ?0.25 v = 12.0 ?0.5 v pp cc oe address = 0 n = 0 latch address + 1 address ? latch address + 1 address ? address + 1 address ? latch latch n + 1 n ? set page prog./verify mode v = 12.5 ?0.3 v v = 6.25 ?0.25 v pp cc address + 1 address ? nogo go yes nogo no no verify end fail read all address n = 10? last address? set read mode v = 5.0 ?0.5 v v = v pp cc cc go program t = 50 s ?5% pw m yes fast high-reliability page programming flowchart
10 hn27c4000g series dc characteristics (v cc = 6.25 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25? 5?) item symbol min typ max unit test conditions input leakage current i li 2 a vin = 6.5 v/0.45 v output voltage during verify v ol 0.45 v i ol = 2.1 ma v oh 2.4 v i oh = ?00 ? operating v cc current i cc 50 ma input voltage v il ?.1 *5 0.8 v v ih 2.2 v cc v + 0.5 *6 v h 11.5 12.0 12.5 v v pp supply current i pp 70 ma ce = v il notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. v pp must not exceed 13 v including overshoot. 3. an influence may be had upon device reliability if the device is installed or removed while v pp = 12.5 v. 4. do not alter v pp either v il to 12.5 v or 12.5 v to v il when ce = low. 5. v il min = ?.6 v for pulse width 20 ns. 6. if v ih is over the specified maximum value, programming operation cannot be guaranteed.
11 hn27c4000g series ac characteristics (v cc = 6.25 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25? 5?) test conditions input pulse levels: 0.45 to 2.4 v input rise and fall times: 20 ns reference levels for measuring timing: inputs; 0.8 v, 2.0 v, outputs; 0.8 v, 2.0 v item symbol min typ max unit test conditions address setup time t as 2s oe setup time t oes 2s data setup time t ds 2s address hold time t ah 0s data hold time t dh 2s oe high to output float delay t df *1 0 130 ns v pp setup time t vps 2s v cc setup time t vcs 2s ce initial programming t pw 47.5 50.0 52.5 ? pulse width ce setup time t ces 2s data valid from oe t oe 0 150 ns ce pulse width during data latch t lw 1s oe = v h setup time t ohs 2s oe = v h hold time t ohh 2s v pp hold time *2 t vrs 1s notes: 1. t df is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. page program mode will be reset when v pp is set to v cc or less.
12 hn27c4000g series fast high-reliability page programming timing waveform program data latch page program program verify data out valid data in stable page program mode t t t t t lw vrs oes pw ces t ohh t vcs t vps t ohs t ds t dh t oe t df t as t ah t ah t as a2 ?a17 a0, a1 data v v ce oe v v + 1.25 v pp v pp cc cc cc cc v il v h v ih
fast high-reliability programming this device can be applied the fast high-reliability programming algorithm shown in the following flowchart. this algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. 13 hn27c4000g series nogo start address = 0 n = 0 n + 1 n set prog./verify mode v = 12.5 ?0.3 v v = 6.25 ?0.25 v pp cc address + 1 address go yes nogo no no verify end fail read all address n = 10? last address? set read mode v = 5.0 ?0.5 v v = v pp cc cc go program t = 50 s ?5% pw m yes fast high-reliability programming flowchart
14 hn27c4000g series dc characteristics (v cc = 6.25 v 0.25 v, v pp =12.5 v 0.3 v, ta=25? 5?) item symbol min typ max unit test conditions input leakage current i li 2 a vin = 6.5 v/0.45 v v pp supply current i pp 40 ma ce = v il operating v cc current i cc 50 ma input voltage v il ?.1 *5 0.8 v v ih 2.2 v cc v + 0.5 *6 output voltage v ol 0.45 v i ol = 2.1 ma v oh 2.4 v i oh = ?00 ? notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. v pp must not exceed 13 v including overshoot. 3. an influence may be had upon device reliability if the device is installed or removed while v pp = 12.5 v. 4. do not alter v pp either v il to 12.5 v or 12.5 v to v il when ce = low. 5. v il min = ?.6 v for pulse width 20 ns. 6. if v ih is over the specified maximum value, programming operation cannot be guaranteed. ac characteristics (v cc = 6.25 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25? 5?) test conditions input pulse levels: 0.45 to 2.4 v input rise and fall times: 20 ns reference levels for measuring timings: 0.8 v, 2.0 v item symbol min typ max unit test conditions address setup time t as 2s oe setup time t oes 2s data setup time t ds 2s address hold time t ah 0s data hold time t dh 2s oe to output float delay t df *1 0 130 ns v pp setup time t vps 2s v cc setup time t vcs 2s ce initial programming t pw 47.5 50.0 52.5 ? pulse width data valid from oe t oe 0 150 ns note: 1. t df is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
fast high-reliability programming timing waveform 15 hn27c4000g series program program verify address data data in stable data out valid t as t ds t vps t vcs t dh t df t ah t pw t oes t oe v pp v cc v pp v cc v cc v +1.25 cc ce t ds oe optional page programming this device can be applied the optional page programming algorithm shown in the following flowchart. this algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. this programming algorithm is the combination of page programming and word verify. it can avoid the increase of programming verify time when a programmer with slow machine cycle is used, and shorten the total programming time. regarding the timing specifications for page programming and word verify, please refer to the specifications for fast high-reliability page programming and fast high-reliability programming.
16 hn27c4000g series start set page prog latch mode v = 12.5 ?0.3 v v = 6.25 ?0.25 v = 12.0 ?0.5 v pp cc oe address = 0 latch address + 1 address latch address + 1 address address + 1 address latch latch n + 1 n set page prog. mode v = 12.5 ?0.3 v v = 6.25 ?0.25 v pp cc address + 1 address nogo go yes nogo no no verify end fail read all address n = 10? last address? set read mode v = 5.0 ?0.5 v v = v pp cc cc go program t = 50 s ?5% pw m set word prog./verify mode v = 12.5 ?0.3 v v = 6.25 ?0.25 v pp cc page prog. reset v = v = 6.25 ?0.25 v pp cc address = 0 n = 0 address + 1 address program t = 50 s ?5% pw m verify yes last all address? go nogo yes optional page programming flowchart
17 hn27c4000g series dc characteristics (v cc = 6.25 v 0.25 v, v pp =12.5 v 0.3 v, ta = 25? 5?) item symbol min typ max unit test conditions input leakage current i li 2 a vin = 6.5 v/0.45 v output voltage during verify v ol 0.45 v i ol = 2.1 ma v oh 2.4 v i oh = ?00 ? operating v cc current i cc 50 ma input voltage v il ?.1 *5 0.8 v v ih 2.2 v cc v + 0.5 *6 v h 11.5 12.0 12.5 v v pp supply current i pp 70 ma ce = v il notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. v pp must not exceed 13 v including overshoot. 3. an influence may be had upon device reliability if the device is installed or removed while v pp = 12.5 v. 4. do not alter v pp either v il to 12.5 v or 12.5 v to v il when ce = low. 5. v il min = ?.6 v for pulse width 20 ns. 6. if v ih is over the specified maximum value, programming operation cannot be guaranteed.
18 hn27c4000g series ac characteristics (v cc = 6.25 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25? 5?) test conditions input pulse levels: 0.45 to 2.4 v input rise and fall times: 20 ns reference levels for measuring timings: inputs; 0.8 v, 2.0 v outputs; 0.8 v, 2.0 v item symbol min typ max unit test conditions address setup time t as 2s oe setup time t oes 2s data setup time t ds 2s address hold time t ah 0s data hold time t dh 2s oe high to output float delay t df *1 0 130 ns v pp setup time t vps 2s v cc setup time t vcs 2s ce initial programming t pw 47.5 50.0 52.5 ? pulse width ce setup time t ces 2s data valid from oe t oe 0 150 ns ce pulse width during data latch t lw 1s oe = v h setup time t ohs 2s oe = v h hold time t ohh 2s page programming reset time *2 t vlw 1s v pp hold time *2 t vrs 1s notes: 1. t df is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. page program mode will be reset when v pp is set to v cc or less.
option page programming timing waveform 19 hn27c4000g series program data latch page program program verify page program mode t t t lw oes pw t ohh t vcs t vps t ds t dh t oe t ds t as t ah t ah t as a2 ?a17 a0, a1 data v v ce oe v v + 1.25 v pp v pp cc cc cc cc v il v h v ih t ah word program mode program t df t vps t df t vrs t vlw t ces t ces t pw t ohs data in stable data out valid data in stable
20 hn27c4000g series erase erasure of this device is performed by exposure to ultraviolet light of 2537 ? and all the output data are changed to ??after this erasure procedure. the minimum integrated dose (i.e. uv intensity x exposure time) for erasure is 15 w?ec/cm 2 . mode description device identifier mode the device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of eprom. by this mode, the device will be automatically matched its own corresponding programming algorithm, using programming equipment. hn27c4000g identifier code a0 i/o8 ?i/o15 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 hex identifier dg-40 (9) (28) (26) (24) (22) (19) (17) (15) (13) data manufacturer code v il x 0000011107 device code v ih x 10100001a1 notes: 1. v cc = 5.0 v 10% 2. a9 = 12.0 v 0.5 v 3. ce , oe = v il 4. a1 ?a8, a10 ?a17: don? care. 5. x: don? care.

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